1. Field of the Invention
The present invention relates to a unit cell that forms a fundamental unit in a layout of a semiconductor integrated circuit device and further to a wiring method and wiring program using the unit cell, and more particularly, it relates to a unit cell that is used for a gate array type or standard cell type semiconductor integrated circuit device and a wiring method and wiring program using the unit cell.
2. Description of Related Art
Conventionally, semiconductor integrated circuit devices by a gate array type, a standard cell type, and the like for which functional circuit blocks formed by arranging unit cells are arranged in a matrix have existed. In the standard cell type, a functional circuit block 120 is constructed by arranging various types of unit cells (rectangular-shaped regions in FIG. 5) in a matrix, as shown in FIG. 5.
In a first metal wiring layer being a lowermost layer of the respective unit cells, a belt-like power wiring is formed through the unit cells in the X-direction. Therefore, when the unit cells are arranged to construct the functional circuit block 120, power terminals contact with each other between adjoining unit cells, and an X-direction belt-like power wiring 103 called a power rail is wired on the first metal wiring layer. Moreover, in the functional circuit block 120 of FIG. 5, a second metal wiring layer is wired in the Y-direction, a third metal wiring layer is wired in the X-direction, and a fourth metal wiring layer is wired in the Y-direction.
Here, wiring of an auxiliary power wiring to prevent current from concentrating in the power wiring 103 will be described. The auxiliary power wiring is wired on an upper layer of the power wiring 103 in a manner running through the functional circuit block 120 in the Y-direction, and is connected to the power wiring 103.
For example, when signal terminals of the first metal wiring layer are not formed on cell frames of the unit cells, a method for wiring an auxiliary power wiring on the second metal wiring layer being on cell frames in the Y-direction can be considered. This is for preventing a situation that an auxiliary power wiring of the second metal wiring layer hides signal terminals of the first metal wiring layer. However, the X-direction widths of the respective unit cells constituting the functional circuit block 120 take values having no correlation with each other. Accordingly, the unit cells cannot be laid in a manner that X-coordinates of the cell frames are aligned. Therefore, the cell frames cannot be arranged through the functional circuit block 120 in the Y-direction. Consequently, an auxiliary power wiring that runs through the functional circuit block 120 in the Y-direction cannot be formed on the second metal wiring layer by use of the cell frames.
Moreover, as shown in an auxiliary power wiring 104 of FIG. 5, a method for forming an auxiliary power wiring that runs through the functional circuit block 120 in the Y-direction on parts other than cell frames in the Y-direction can be considered. In this case, however, it has been necessary to wire the auxiliary power wiring 104 not on the second metal wiring layer but on the fourth metal wiring layer being a further upper layer by bypassing. This is because, if the auxiliary power wiring 104 is formed on the second metal wiring layer, the signal terminals of the first metal wiring layer are hidden, and a situation that signal wiring cannot be drawn out of the signal terminals can consequently occur.
As the above-described related arts, Japanese unexamined patent publication No. 2004-71878 and Japanese unexamined patent publication No. 1986(S61)-207031 have been disclosed.